1. Field of the Invention
This invention relates to semiconductor memory devices, circuits for decoding address busses for memory devices, and circuits for selecting one of a plurality of memory devices in response to addresses provided on an address bus.
2. Description of the Prior Art
Typical microprocessor systems include a microprocessor having an address bus which defines a memory address space. The address bus is coupled to a plurality of memory devices such as EPROMs and static RAMs and an address bus decoder. The address bus decoder generates a plurality of chip select signals for selecting one of the memory devices, thereby mapping the memory devices into selected blocks of addresses within the memory address space. Unfortunately, as described below, the address decoder adds to the delay between the time an address is provided on the address bus and the time data is provided by the memory devices because the memory devices cannot begin read operations until they are selected by the decoder.
FIG. 1 illustrates a typical prior art microprocessor system which includes a microprocessor 10 having an address bus 12 and a bidirectional data bus 14 used to facilitate the transfer of data between microprocessor 10 and memory devices 16 and 18. Memory devices 16 and 18 are typically static RAMs, EPROMs, EEPROMs, or other conventional memory devices. A decoder 20 maps the address space of memory devices 16 and 18 into the memory address space defined by address bus 12. Thus, FIG. 1a illustrates the memory address space 21 defined by address bus 12. In the illustrated circuit, memory device 16 is a 2k word memory device mapped into address block 17, while memory device 18 is a 2k word memory device mapped into address block 19.
The circuit of FIG. 1 is typical of systems in which device 16 is one type of memory device (e.g. an EPROM) and device 18 is another type of memory device (e.g. static RAM). The circuit of FIG. 1 is also typical of systems in which devices 16 and 18 are the same type of memory device (e.g. EPROMs) because if one desired to have two noncontiguous address blocks of EPROM memory in address space 21, this typically requires two EPROMs and a decoder.
Of importance, when microprocessor 10 accesses a location in one of memory devices 16 and 18, an address is placed on address bus 12, and the address is decoded by decoder 20 which determines whether the address corresponds to a location within memory device 16 (i.e. an address within address block 17), a location within memory device 18 (i.e. an address within address block 19), or an address location within a device (not shown) other than devices 16 or 18. If the address to be accessed by microprocessor 10 corresponds to a location within memory device 16, decoder 20 provides a signal CE1 on an enable line 22 to thereby enable memory device 16. Conversely, if the address accessed by microprocessor 10 corresponds to a location within memory device 18, decoder 20 provides a signal CE2 on an enable line 24 to thereby enable memory device 18. Signals CE1 and CE2 cause devices 16 and 18 to power up their respective sense amplifiers (not shown). If devices 16 and 18 are EPROMs or EEPROMs, signals CE1 and CE2 also cause devices 16 and 18 to ground the memory cell source regions. For the case of a static RAM, signals CE1 and CE2 are also logically ANDed with a write enable signal generated by microprocessor 10 (not shown). Thus, for example, if device 16 is a static RAM, write operations cannot be performed by device 16 unless both the CE1 signal and the write enable signal are active.
Address bus 12 is also coupled directly to memory devices 16 and 18 to select individual locations within memory devices 16 and 18. In some prior art memory devices, signals CE1 and CE2 also enable the memory device address input buffers.
When microprocessor 10 reads data from memory device 16 or 18, an output enable signal OE is asserted on an enable line 26 by microprocessor 10, which causes the selected memory device to drive data bus 14 with appropriate data. (Signal OE is used to control whether the data output buffers of devices 16 and 18 are three-stated, but is logically ANDed with signal CS1 by an AND gate within device 16 and with signal CS2 by an AND gate within device 18 so that devices 16 and 18 can only drive data bus 14 when they are selected.)
Although FIG. 1 illustrates only two devices coupled to microprocessor 10, microprocessor systems typically include other memory devices, including EPROMs, ROMs, static RAMs, or peripheral devices such as I/0 devices.
FIGS. 2a to 2e illustrate the timing of the various signals generated in FIG. 1. Referring to FIG. 2a, at time T1, microprocessor 10 drives address bus 12 with an address corresponding to a location within memory device 18. Thereafter, decoder 20 recognizes the address on address bus 12 as corresponding to a location within memory device 18 and at time T2, causes signal CE2 on output line 24 to go active (low) and ensures that signal CE1 on line 22 is inactive (high). Time delay T.sub.AAD represents the propagation delay between the time an address is received by decoder 20 and the time decoder 20 asserts (i.e. holds active) either signal CE1 or signal CE2. A predetermined time period (T.sub.OE) after microprocessor 10 asserts the address on address bus 12, microprocessor 10 then asserts output enable signal OE on line 26. Thereafter, at time T3, memory device 18 provides data on data bus 14. Of importance, memory device 18 exhibits a propagation delay T.sub.AAM between the time signal CE2 is asserted and the time memory device 18 provides data on data bus 14.
The total time delay between the time an address is asserted on address bus 72 and the time memory device 18 provides appropriate data equals T.sub.AAD plus T.sub.AAM. It would be desirable to eliminate or reduce this time delay to enhance the speed of the microprocessor system.